Message exchange system utilizing time multiplexing and a plurality of different sized revolvers



Jan. 24, 1967 MESSAGE EXCHANGE SYSTEM U'IlLlZlNG TIMIJJ MULTIPLEXING AND A PLUHALITY OF DIFFERENT SIZE?) REVOLVERS Filed Aug. 20, 1963 FIG.3

H. G. HOEHMANN BEGINNG 11 CONTAROE q; ADDRESS ADDRESS [CHARACTER {L i "ACF" CONTROL MESSAGE iCHARACTER FIG.2

MESSAGE CHARACTER I CHARACTER CONTROL CHARACTER EXCHANGE 13 Sheets5heet 1 FOG.

E g -J'1 3 INVENTORO HENRY G HOEHMANN ATTORNEY Jan. 24, 1967 H HQEHMANN 3,300,763

MESSAGE EXCHANGE S YSTEM UTILIZING TIME MULTIPLEXING AND A PLURALITY OF DIFFERENT SIZED REVOLVERS Filed Aug. 20, 1963 15 Sheets-Sheet 2 j 1CD 500; CHE'RDD DELAY LOW $005 110 M5 09 TRANSDELAYTD M in ,1 gmr x REDOGNIHON CONTROL TRAN5PORT 956D NPUT LOGIC GATE LOGIC DELAY LQGICfiUUTPUT L L L 'T J 105 I CONTROL 1520 CONTROL DELAY CD DELAY LOGIC AH STORAGE 95 IjSTORAGE DELAY so J21 DELAY LOGIC H2 i IL SINGLE CHARACTOR ADDRESS W REF REF m s L I 3 5 2 0/ NINERPM THREE RPM FIG. 6A

ROW comp g 5 4 5 6 v a 9 to u Dl S Kli g 5 4 s a a 9 i n JTDISIQS 1 3 1 5 1 2 5 i c i Z 5 2 5 4K iJl U Row comm; g g 0 p! D ISKS i 2 Q, i D, r V n Jan. 24, 1967 H. G. HOEHMANN MESSAGE EXCHANGE SYSTEM UTILIZING TIME MULTIPLEXING AND A PLURALITY OF DIFFERENT SIZED REVOLVERS Filed Aug. 20, 1963 13 Sheets-Sheet 3 NOE TL -l i -2 2 2- aosavw a a 2 a e H. G. HOEHMANN Jan. 24, 1967 MESSAGE EXCHANGE SYSTEM UTILIZING TIME MULTIPLEXING I AND A PLURALITY OF DIFFERENT SIZED REVOLVERS Filed Aug. 20, 1963 13 Sheets-Sheet 9 CNARACYER APPEARANCE;

W WW W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W M W W W W W W W W W W W W W W W W W W W W W W W W W W W OWOWO 0 0 0 1 1| 1. A IAt 41: W W W W W W W W W W W W W WU OWOWOWO O O O OWOWOWO W W WO W W W W W W W Kw W W W W W W W W W W WI W W I W E O AU UWO AURU O OOWAU U O OWU W W W W AU W W W W W W W W W W on W W W D W WO AU OWOWOWO OWO OW OWO OWOW JWW D W W W W W W W W. W W A W W W W W W W W W W .W W W W W W W W W 1 1 WO O W WOWOW W WO OWOW T SEVEN BIT APPEARANCE TD AND SD lNPUI-OUA PUT STAUON W W W W W W W W W W W W W W W W W W WOW Wi W W W W |+1WiW0WOWl|1 W W W W W W W W W W W W W L IL SIX BIT CODE USED FOR TRANSMISSION 0 i i O 0 W 0 0 BINARY BITS A REPRESENTED AKLGAAALE ADDRESS CHARACTERS RtSWVA'HON A lSIORAGE o;

SECQND ADDRESS EWCHARACTER /STORAGE 0F FIRSTAADERESS W W. CHAR m H A n WW as m H6 as a4 H5 B2 A FIGHE Jan. 24, 1967 H. G. HOEHMANN 3,300,753

MESSAGE EXCHANGE SYSTEM unmzmc TIME MULTIPLEXING AND A PLUHALITY OF DIFFERENT SIZED REVOLVERS Filed Aug. 20, 1963 13 Sheets-Sheet 10 i ms T201 I 1H 1 402 ,405 AND A gm AND OR 403 L 406 404 J24 J16? AND AND 1 L f L m 1' 7 u A Jan. 24, 1967 H. G. HOEHMANN 3,300,763

MESSAGE EXCHANGE SYSTEM UTILIZING TIME MULTIPLEXING AND A PLURALLTY OF DIFFERENT SIZED REVOLVERS Filed Aug. 20, 1963 13 Sheets$heet 11 1 l 1 425 J WA m 755W A J52 409 u T36 m Wi" /426 n- AND E i Q; 5

TRI Us I 42? 1 :iimj AND i: 0 1 434 n11 l 45 416 an OR *-1 5 m5 s a s s R AND W w mu; TRIG mo 45? 455 L 1 0] L 0] 0 1 440 i {T1098 V i if AND 436 l i 5 35s i L mesa L 0R 950mm 1 l P l 1 1 F. i i 1 i in i H ,p-

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1 1 1 w I 460 m 1 C 11-2 1 k 1*" OR I i i J Jan. 24, 1967 H. G. HOEHMANN 3,300,763

MESSAGE EXCHANGE SYSTEM UTILIZING TIME MULTIPLEXING AND A PLURALITY OF DIFFERENT SIZED REVOLVERS Filed Aug. 20, 1963 13 Sheets-Sheet 13 ML 0R 1 FIG. 18A 1 1 t 01- 521 0 330 OR AND 5038 551 F I T 525 T R R i k f 5 B7 B7 552 522 AND A AND I 51511 1 1-5050 00 88 FIG. 18C FIG. 18B

United States Patent Otilice Patented Jan. 24, 1967 3,300,763 MESSAGE EXCHANGE SYSTEM UTILIZING TIME MULTIPLEXING AND A PLURALITY ()F DIF- FERENT SIZED REVOLVERS Henry G. Hoehmann, Los Gatos, Calif., assignor to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Aug. 20, 1963, Ser. No. 303,340 9 Claims. (Cl. 340-1725) This invention relates to communications systems. More particularly, this invention relates to communicntions systems which have a large number of independent terminal stations for sending and receiving messages.

In general, terminal stations (i.e., input-output devices) operate at relatively low speed. That is. the speed of input-output devices is low compared to the speed of modern data processing equipment. For example, the time between characters generated by a manually operatcd typewriter keyboard is in the order of magnitude of tenths of a second. In contrast, the time required to accomplish a switching operation in a modern electronic data processing system is in the order of magnitude of millionths of a second. Hence, if one or more conven tional input-output devices are connected to a modern high speed data processing system, the data processing system can perform a large number of switching operations between each signal from the input-output devices.

The present invention provides a special purpose data processing system which can be used as a low cost exchange for a communication system which has a large number of input-output devices. The essence of the invention lies in the organization system whereby a relatively inexpensive data processing system can efficiently accomplish all the needed storage and switching functions for a large number of input-output devices.

The system of the present invention includes a queuing buffer in each input-output channel and an exchange which is common to all the channels. The queuing buffer in each channel receives messages asynchronously from the associated input-output station, it establishes and stores an input queue tie, a list of messages) and, it feeds message characters on a synchronous basis to the exchange. The queuing buffer in each channel also receives message characters on a synchronous basis from the exchange, it establishes an output queue and, it feeds the message characters to the associated input-output station.

The exchange operates synchronously based upon a machine cycle which allocates a plurality of character times to each channel. During one particular character time during each machine cycle, a character can be transferred from the queuing buffer associated with each channel to the exchange and during the same character time, a character can be transferred from the exchange to the queuing buffer associated with the particular channel.

The exchange includes a plurality of repeaters (i.e., circulating storage elements) which repeat information stored therein at preestablished intervals. These repeaters store both control information and message characters. By correctly matching the length of the delays introduced by the various repeaters and their synchronization, the correct control information and the correct message characters are available at optimum times, thereby requiring a minimum amount of control circuitry.

The object of the present invention is to provide an improved message exchange system.

A further object of the present invention is to provide a low cost message exchange system.

Yet another object of the present invention is to provide a system for directing a message from a transmitting station to one or more receiving stations.

Still another object of the present invention is to provide etlicicnt means for transferring messages from a sending queue to one or more receiving queues.

Yet another object of the present invention is to provide a low cost message exchange system for a plurality of slow input-output stations by using a relatively high speed data processing system.

Yet another object of the present invention is to provide a high speed message exchange system having few components for handling the messages being transmitted between a relatively large number of terminals.

Yet another object of the present invention is to provide a message exchange system having relatively few components which can simultaneously handle the exchange of messages between a relatively large number of terminals.

Yet another object of the present invention is to provide a high speed message exchange system having few components which can simultaneously direct a plurality of messages between a plurality of terminals.

A still further object of the present invention is to provide a message exchange which responds to address characters at the beginning of each message, establishing a route therein so that message characters which follow are directed to the appropriate output stations.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, illustrated in the accompanying drawings.

FIGURE 1 is an overall schematic diagram of the system.

FlGURE 2 shows the format of messages transferred through the system.

FIGURE 3 is a timing diagram showing the times at which messages are transferred between the memory and the exchange shown in FIGURE l.

FIGURE 4 shows the format of each character in the system.

FIGURE 5 is a schematic diagram showing the major components in the exchange shown in FIGURE 1.

FIGURE 6A shows three rotating disks having characters recorded thereon.

FIGURE 6B is a chart showing the synchronization between the disks shown in FIGURE 6A.

FIGURE 6C is a simplified form of the chart shown in FIGURE 6B.

FIGURE 7 is a chart which shows the synchronization between various components in the exchange shown in FIGURE 5.

FIGURE 8 is an expanded portion of the chart shown in FIGURE 7.

FIGURE 9 is a chart used to explain the address setup mode of operation.

FIGURES 10a and 10b (which fit together as shown in FIGURE 10) are a schematic diagram showing the details of control delay logic.

FIGURE 11A is a schematic block diagram of the control delay logic.

FIGURE 11B is a chart showing the use of the various bits in each character stored in the control delay element.

FIGURE llC is a chart showing the various forms of addres es associated with each input-output station.

FIGURE llD is a chart showing the conversion between dilferent forms of address characters.

FIGURE 11F. is a chart showing how the various bits in each character stored in the storage delay element are used.

FIGURE 11F is a schematic diagram showing the details of the storage delay logic,

FIGURE 12 is a schematic circuit diagram showing the details of the control gate logic.

FIGURE [3 is a schematic circuit diagram showing the (ohutui I. General Description:

A. Message Trans-[er .\intte s it. Address Setup Mode it t. Adtlrc. l we Morita. 1|

I1. Iutcrcouuct suns ltetwt-cn Major Components in Exchange 1021 A. Recognition Logic 1107. .1 12 it. toutrul (iat.c113 12 1. Single Character Delay Logic 1 13 l). 'lrauspnrt lh'lay Logic 109. 13 1C. i iuglc (Iutruvt- Number (outpurzttur115.. 13 l. Queue itleutti ion Counter 11!]. 1i ti. fuldrcsst'iontp aturllT.. V i 111. Detailed Description of Circuitry:

A. 'liiuer 15 1%. Address Numbering Scheme, lti t. (untrul Delay Logic 111 and (outrol Delay 1 l 17 I). Hturuuc Ueluyhl) up. H, (outrol tintcLoyie 113. 23 I Multiplexing Logic 101. 2'1 ti. 'lruusttort. licltty Logic 100. 24 It. Singl thttrtuicr Number (outpartttor 1th. 1 25 Address tompuratitr llT 2H J. (Jut-ue ltltnthicutiuu (winter 1159. W. T l\'. Mcssugv Recognition Logic. N L. Queuing Memory: H 20 1\'. (itlttl'tll Fuiuuutry:

A. Aritlrtss Setup Motle, 31 I5. Mes age Transfer Mode... t". Address litust )itttitL.

General description An overall block diagram of a preferred embodiment of the invention is shown in FIGURE l. it includes ninety five input-output stations designated L1 to 1.95. a queuing memory 101 and an exchange 102. Each of the stations L1 to L95 can transmit and receive messages. Fach me sage include (a) control characters (/1) addr s characters and (0) message characters in the format shown in FIGURE 2. The first character in each message is a control character AfF. The control character AtfF is followed by a number of address characters which designate the particular station or stations to which the message is directed, The address characters are followed by a control character MCF which designates that there are no further address characters in the message. The control character MCF is followed by the mes age char acters which form the message proper. The last message character is followed by a control character EM which indicates that there are no further characters in the mes age.

Queuing memory 101 temporarily stores messages transmitted by the various stations and it makes the characters in each message avaiiable to the exchange 102 on line 104 on a synchronous timeshared ba is. in general when memory 101 makes a character available to exchange 102 it is not dcstroycdfbut instead memory 101 rccirculates the character so that after the last character of a message is made available to exchange 102. the first character in the message is again made available to the exchange. However. when memory 101 receives a signal on control line 106 the last character transmitted and the two preceding characters of the same message are destroyed (i.e.. not recirculated). Memory 101 thus pro vides a recirculating queue or list of characters for each channel. On a signal from exchange 102 via line 106 three characters previously supplied to exchange 102 are deleted from the queue, that is, the queue associated with a particular input-output station is shortened by three characters.

Characters from the various input stations are sent to the exchange 102 on a time multiplex basis over line 104 and the characters directed to the various output stations are returned to memory 101 on a time multiplex basis over iine 105. The time a character appears on line 104 indicates the station where the character originated and the time a character appears on line 105, indicates the station to which the character is directed. Exchange 102 temporarily stores the various characters for amounts of time controlled by the address at the beginning of the 2581)- ciuted message, thereby directing the characters to the stations designated by these address if these stations are free to receive the characters.

For example, at one particular time a message from line 1 which is stored at queuing memory 101 may be in the process of being transmitted through exchange 102 to lines 4, )4 and 95. While this message is being trans mitted to lines 4, 94 and 95 queuing memory 101 may receive a message from line 5 which is directed to lines 1 and 94. Since line 94 is busy receiving the message from line 1, the second message when it is sent through exchange 102 is only directed to line 1 and the message is recirculated in memory 101. Thereafter when line 94 is free the message is again sent through exchange 102 to line 94.

The time multiplex basis on which messages are transferred from queuing memory 101 to exchange 102 and back to queuing memory 101 i shown in FIGURE 3. The memory 101 and the exchange 102 operate based upon a cycle which has one thousand five hundred and twenty (1520) character times. One character can be transmitted from queuing memory 101 to exchange 102 and vice versa every sixteen character times. This is shown in FIGURE 3. During character time one a mes sage character which originated at station L1 can be transmitted to exchange 102 and a character directed to station Ll can be transmitted from exchange 102 to memory 101, during character time seventeen a message character which originated at station L2 can be transmitted to exchange 102 and a character directed to station L2 can be transmitted from exchange 102 to memory 101, etc. until at character time one thousand five hun drcd and five (1505) a character which originated at station L95 can be transmitted to exchange 102. A second character which originated at station L1 can be transmitted to exchange 102 in the first character time of the next cycle, etc. The first character time of the next cycle follows character time one thousand five hundred and twenty (1520).

Control signals can only be transmitted on lines 106 and F during the ninetyfive character times which are associated with input-output stations (shown in FiG- URE 3). A signal on line 106 during a particular character time indicates that the recirculating message in memory 101 (i.e., the queue), which is associated with the character time during which the signal is sent should be shortened by three characters. A signal on line F during a particular character time indicates that the input output station associated with the particular character time has a message in memory 101 which is ready for transmission to exchange 102. It should be particularly noted that during fifteen out of each sixteen character times no characters are being transmitted from the queuing memory 101 to exchange 102 or from exchange 1.02 to queuing memory 101. As will be seen in detail later. these character times are used for internal manipula lions within exchange 102.

Each character time is divided into eight bit times as shown in FIGURE 4. In general, the first seven bit times in each character time are used to transmit either it control character, an address character or a message character and the eighth bit time is used for control purposes. The bit times are designated B1 to B8.

The time that a character appears on line 104 indicates which input station transmitted the character and the time that a particular character appears on line 105 designates the particular station that will receive the pan message mode.

ticular character. Hence, the general function of exchange 102 is to delay characters by appropriate amounts. Furthermore, in order to send a particular character to a plurality of stations, the character must be repeatedly transmitted over line 105 at the correct times. In order to perform the above functions, exchange 102 includes nine synchronized delay elements of various lengths.

FIGURE 5 is an overall schematic diagram of exchange 102 showing the major elements therein. There are six single character delay elements designated SCDI to SCD6, a transport delay element designated TD, a control delay element designated CD and a storage delay designated SD. Single character delay elements SCDl to SCD6 are each one character long. That is, if the bits of a particular character are sequentially introduced into the input of any one of these delay elements at a particular time they sequentially appear at the output thereof one character time later. Transport delay element TD is ninety-five (95) characters long. Control delay element CD is one thousand five hundred and twenty (1520) characters long. and storage delay SD is ninety-five (95) characters long. Each of. the ninetyfive positions on storage delay SD and each of the one thousand five hundred and twenty positions on control delay CD is uniquely associated with a particular one of the 95 input-output stations L1 to L95. The association between the positions on storage delay SD and on control delay CD and the input-output tations will be explained later.

Each of the nine delay elements has logic associated therewith which controls the signals applied thereto and received therefrom. The logical circuitry which controls the delay elements SCD1 to SCD6 is designated 107 and the logic associated with transport delay TD, control delay CD, and storage delay SD is respectively designated 109, 111, and 112. The other major components in the system are recognition logic 110, control gate logic 113, single character delay number comparator 115, address comparator 117, queue identification counter 119 and timer 121.

Characters which are sent from memory 101 to exchange 102 first go through recognition logic 110 (see FIGURE 5). Recognition logic 110 detects the control characters and in accordance therewith sets the circuitry in exchange 102 in the condition to handle the following characters.

The operation of the exchange 102 is in general divided into three separate and distinct modes which are respectively termed the address setup mode," the message mode and the address erase mode. The system is in the address setup mode while it is processing that portion of a message between control characters ACE and MCF (see FIGURE 2). During the address setup mode, control bits are set at appropriate places in control delay CD and storage delay SD so that when the system subsequently goes into message mode each message character will be made to appear on output line 105 at the appropriate times. Stated differently, during the address setup mode a route is established or enabled for the characters which are subsequently transmitted during a During the address erase mode the previously established route is disenabled or obliterated.

The synchronization which exists between the characters stored in the various delay elements is shown in FIG- URE 7. FIGURES 6A, 6B and 6C will be used to explain FIGURE 7. FIGURE 6A shows a large revolving disk L which has nine characters designated I to 9 recorded around its periphery, a medium-sized disk S which has three characters designated 1 to 3 recorded around its periphery and a very small disk T which has one character recorded on its periphery. Each of the characters is equal in length; however, for convenience of illustration the characters on the layer disks are shown as being compressed. Disk L revolves at a speed of one revolution per minute, disk 5 revolves at a speed of three revolutions per minute and disk T revolves at a speed of nine revolutions per minute. A stationary reference arrow is associated with each disk. This reference arrow could be a combined read-write head.

FIGURE (:15 describes the synchronization of the disks shown in FIGURE 6A. For ease in reference the columns in FIGURES 6B and 6C are numbered and each row is given a difiercnt letter designation. FIGURE 6B shows which characters on disks L and S are passing the reference arrows at any particular time. For disk T the same character is always passing a reference arrow since there is only one character on the disk. Row L in FIG- URE n8 is used to show the length of time tie. the number of revolutions) that a particular character remains recorded on disk T. For example. column 5 in FIGURE 6.8 shows that when character position live on disk L is passing the associated reference arrow, character position two on disk S is passing the associated reference arrow. Row 0. column 5. indicates that this is the Iirst time that the character then recorded on disk T has passed the ussocialcd reference arrow.

Thc horizontal axis in FIGURE 68 can be considered as designating the various character times through which the system passes and the numbers in the various columns may be considered us designating the state of each disk (i.e., the orientation of each disk) at that particular character time.

FIGURE 6C shows an abbreviated form of the chart shown in FIGURE 68. In the chart of FIGURE (1C certain of the numerals are omitted and only the numerals of particular interest are shown. Where two numerals are connected by a dashed line. it indicates that the intervening numerals have been omitted. The fact that a disk has started a new cycle is indicated by an encircled number such as in number 3" in row 11 between columns 1 and 2. The point at which new cycles start is always shown. The format of FIGURE 7 is the same as that of FIGURE 6C.

Each of the delay elements shown in FIGURE 5 can be used as a revolving storage element. A character which is introduced into the input of a delay element appears at the output thereof a certain number of character times later and as each character appears at the output it can be recirculated to the input by the associated logic. At any particular time only one character position is available to the associated logic. This is equivalent to the fact that at any one particular time only one character position is adjacent to each reference arrow in FIGURE 6A. (n.b. the above is a generalization that is subject to certain exceptions which are pointed out in detail later.) The synchronization which exists between the various delay elements shown in FIGURE 5 is shown in FIG- URE 7.

Similar to FIGURE 68. in FIGURE 7 each different column represents a different character time in the machine cycle. Since both the machine cycle and the control delay CD have one thousand five hundred and twenty (1520) character times. the particular character position of the control delay CD being read at any particular time (shown in row 1 of FIGURE 7) also gives the point in the machine cycle represented by the particular column. For ease in illustration the character times between positions two hundred and twenty-five (225) and one thousand four hundred and eightymine (I489) which lies between columns 15 and 16 have been omitted.

During each machine cycle exchange 102 can receive one character and transmit one character to each of the ninety-five input-output stationsv Those character times during which characters are transmitted between memory 101 and exchange 102 (see FIGURE 3) are hereinafter designated line times. The particular input-output station assoicated with each line time is shown in row 2 of FIG- URE 7. Rows 3 and 4 of FIGURE 7 show how the positions on transport delay TD and storage delay SD are 7 synchronized with the one thousand five hundred and twenty (152(3) positions on control delay CD and with the signals from the various input-output stations. Signals from and to station L1 are received and transmitted during the first character time of each cycle (see FIG- URE 2). This is during the first character time of control delay CD and during the first character time of transport delay TD and storage delay SD (see column 1. FIG- URE 7). Ninety-six character times later input-output station 7 is being serviced, control delay CD is at position ninety-seven and transport revolver CD and storage revolver SD are at position two (see column 7 of FIGURE 7). Ninety-six character times later inputoutput station 13 is being serviced. control delay CD is at position one hundred and ninety-three (193) and transport delay TD and storage delay SD are at position three (see column 13). The transport delay TD and stonage delay SD go through sixteen cycles during each machine cycle, i.e., during each cycle of control delay CD. During the first cycle of the tuansport delay TD and storage delay SD a line time occurs during the first character time of transport delay TD and storage delay SD and no line times occur during character times two to sixteen inclusive of transport delay TD and storage delay SD. During the second cycle of transport delay TD and storage delay SD line time 7 occurs during character time two of transport delay TD and no line times occur during character times three to seventeen of transport delay TD and storage de lay SD (see columns 6 and 7). During the third cycle of transport delay TD a line time occurs during the third character time oi transport revolver TD and storage delay SD (sec column 13, etc). Each character time of transport revolver TD and of storage delay SD is uniquely associated with one particular line time and this character position in transport delay TD and storage delay SD is only available during that line time. For example. character position one on transport revolver TD is associated with line time 1, character position two on transport re yolver Ti) is associated with line time 7, character position three on transport revolver TD is associated with line time T3. etc. Likewise. each character position on storage delay SD is associated with one particular line time.

Rows 5. 6. 7. 8, 9 and ID in FIGURE 7 relate to single character delay elements SCDI to SCD6. Since each single character delay element SCDI to SCD6 only stores one character. the character stored therein is available during each character time. For reasons which will be explained in detail later. when a particular character is stored in a particular one of the single character delay elements SCDi to SCDfi, it is allowed to remain therein for ninety-six (96) character times. Thus, each character stored in a single character delay element is available for ninctysix character times. The points in the machine cycle during which the characters in the single character delay elements SCDl to SCDfi are changed is shown in rows to 10 of FlGURE 7. A new character is placed in a single character delay element during each character time which is indicated by a l in the associated column or FIGURE 7. For example. column 2. shows that a new character is placed in single character delay element SCDl during character time seventeen. column 8 ShOWS that a new character is placed in single character delay element 5CD] during character time one hundred and thirteen (113). etc. it should be particularly noted that during the next machine cycle (beginning in column 18) a new character is not placed in single character delay element SCDl during character time seventeen. Instead, a new character is placed in single character delay element SCDI during character time thirty-three (33). During the first machine cycle single character delay element SCDZ is beginning a new cycle at line time one; however, during the next machine cycle single character delay element SCDZ is beginning a cycle at line time two. If the chart were continued, it would be noted that during the third machine cycle single character delay element SCD4 would be beginning a new cycle at line time one.

Likewise, the line time two coincides with the beginning of a cycle in single character delay element SCDI. whereas during the second machine cycle line time two (column 19) coincides with the beginning of a new cycle of single character delay element SCD2.

The manner in which the system Operates during message mode, address setup mode" and address erase mode will now be explained. Thereafter the details of the various operations will be explained. The system can be in address setup relative to one input-output station, it may be in message mode relative to a second input-output station, it may be in address setup mode relative to a third input-output station and in address setup mode relative to a fourth input-output station. etc. at the same time. The system is designed such that the operation taking place with respect to one line cannot interfere with the operations taking place with respect to the other lines.

Message transfer mode The manner that message characters are transferred from input 104 to output 105 will now be explained. Each message character is received on input 104 at a particular time. It is stored in one of the single character delay elements SCDl to SCD6 and it remains in the particular single character delay element for ninety-six (96) character times. Information stored on control delay CD causes the character to be transmitted from the single character delay element to the transport delay element TD at various times so that it will eventually reach output line 105 at the appropriate times.

Each character position in control delay CD can store information which will initiate the transfer of information from a particular single character delay element to the position then available on the transport delay element TD. The information stored on the control delay element CD is the number of a particular single character delay element. For example. if in position one hundred and seventy-seven (177 of control delay CD (sec column 12 of FIGURE 7) a number indicating single character delay element SCD4 is stored, then during character iiltlc one hundred and seventy-seven (177) the character stored in single character delay element SCD-l is transferred to character position eighty-two (82) on transport delay element TD. Column 12 in FIGURE 7 shows that character position eighty-two (82) on transport delay TD is the character position available at character time one hundred and seventy-seven (177).

The path which characters follow is from input 194 to one of the single character delay elements to transport delay TD to output 105. The particular single character delay element wherein each message character is stored is the particular single character delay element which is beginning a cycle during the character time that message characters are received. For example. column 2 in FIGURE 7 shows that line time two occurs at character time seventeen (17), that is. column 2 shows that during character time seventeen (17) a message Cl'l'z'lf'lClCl' can be received from line two. Column 2 further shows that during character time seventeen (17) single character delay element SCDl is beginning a new cycle. Message characters from a particular input station do not always use the same single character delay element. For example, column 19 in FIGURE 7 shows that during the next machine cycle the message character received from input-output station 2 is placed in single character delay element SCD2. In general, the message character received from a particular input-output station sequentially uses the six single character delay elements SCDl to SCD6. That is, if the first character from a particular input station first uses single character delay SCDI. the next character from this station will use single charac ter delay SCD2, the next character will use single char- 9 acter delay SCD3, etc. After single character delay SCD6 is used, the next character again uses single character delay SCDl.

An example will now be given of how exchange 102 transfers a message character from input-output station L7 to input-output stations L2 and L15.

The message character from station L7 is received by exchange 102 (FIGURE 1) on line 104 at character time ninety-seven (97) (see column 7 of FIGURE 7). Exchange 102 must transmit the character on line 105 at character time seventeen (17) for input-output station L2 (see column 2 of FIGURE 7) and at character time 225 for input-output station L (see column 15 of FIGURE 7). FIGURE 8 shows the details of each character time between character time ninety-seven (97) and character time one hundred and thirty-two (132), that is, FIGURE 8 shows in detail that portion of FIG- URE 7 which lies between columns 7 and 9.

During a previous address setup mode, information was recorded on control delay CD indicating that the next message character received during line time seven was to be transmitted on output line 105 at line times two and fifteen. This information was recorded in character positions one hundred and twelve (112) and one hundred and thirty (130) of the control delay CD. (What information is recorded and how it is recorded will be explained later.) The information is indicated by the X in rows 117, columns 16 and 34, of FIGURE 8. The character received during line time seven (character time ninety-seven) is stored in single character delay SCD2 which is just beginning a new cycle. The character remains in single character delay SCDZ for ninetysix (96) character times. This is indicated on row 6b of FIGURE 8. At character time one hundred and twelve (112) the information recorded in control delay CD actuates a transfer mechanism (which will be described later) which transfers the character stored in single character delay SCD2 to transport delay TD. Likewise, the information recorded in position one hundred and thirty (130) of control delay CD causes the information stored in single character delay element SCD2 to be transferred to position thirty-five (35) of transport delay TD during character time one hundred and thirty (130). This is indicated by the B in now 3b, columns 16 and 34, of FIGURE 8. The above explanation shows how a character is transferred from an input line to a single character delay element and from there to the transport delay element TD. Once information is on the transport delay element TD it is transferred to the memory 101 on line 105 the next time the particular character position of transport delay element TD coincides with a line time. For example, the information stored at character position thirty-five (35) in transport delay TD is transmitted to output line 15 during character time two hundred and twenty-five (225) (see column 15 of FIGURE 7) and the information stored in character position seventeen (17 of transport delay TD is transmitted to line 2 at character time seventeen (17) of the next cycle (see column 19 of FIGURE 7). Character positions seventeen (17) and thirty-five (35) on transport delay TD do not coincide with a line time at any character time previous to character times two hundred and twentyfive (225) and seventeen (17) as set out above.

The above described how one message character is transferred through exchange 102. A plurality of other message characters from other lines and to other lines may be simultaneously handled by exchange 102 and there will be no interference between them.

Address setup mode The general operation of the system during the address setup mode will now be explained by use of FIGURE 9 which shows the synchronization which exists between certain selected elements at character time ninety-seven (97) during seven different machine cycles (columns 1,

10 2, 3, 9, 11, 13 and 19 of FIGURE 9). It also shows the synchronization at certain other selected character times during the various cycles.

Each address contained in a message consists of three address characters. Hence, exchange 102 must accumulate three characters from a particular input station before it can determine what an address is. This is indicated by columns 1, 2 and 3 in FIGURE 9. Column 1 indicates that a first address character is received from station L7 during character time ninety-seven (97). This character is stored in character position two (2) on storage delay SD. During the next machine cycle (column 2) a second address character which is part of the same address is received during character time ninety-seven (97) and this is again stored in character position two (2) on storage delay SD. Character position two (2) on storage delay SD is now storing two address characters. This is done by a reduced code which will be explained in detail later. The storage of address characters in storage delay SD is indicated by the A and A in row 4!). During the third cycle the third address character of the particular addresses is received during character time ninety-seve11 (97) and by combining the third character with the two characters stored in position two (2) on storage delay SD the address proper is generated. This address is stored in the single character delay element then beginning a cycle. In the particular example shown single character delay element SCD3 is then beginning a cycle. Hence, the address herein designated by the capital letter C on row 70 is stored in single character delay element SCD3. This address remains in single character delay element SCD3 for ninety-six (96) character times, i.e., for ninety-six (96) cycles of single character delay element SCD3.

As explained previously, each character position on transport delay TD is associated with a particular inputoutput station, i.e., with a particular line time. When the character position in transport delay TD which is associated with the station whose address is C appears, the number of the single character delay element which will be associated with that input station during the next cycle is written on the control delay element CD. In the particular example shown in FIGURE 9, the address is that of station L2. By examining column 2 of FIGURE 7, it is noted that character position seventeen (17) on transport delay TD corresponds to station L2. Hence, when character position seventeen (17) of transport delay TD appears (column 4 of FIGURE 9) the number of the single character delay element which will be associated with this station during the next machine cycle is written on the position of control delay CD then available. In this case the number SCD4 is written in position one hundred and twelve (112) of control delay CD. For reasons which will be explained later the number written on the control delay is always one greater than the number of the single character delay element wherein the number is stored. In the example shown the address C is stored in SCD3 and the number of SCD4 is written on the control delay. During the next three cycles, three more address characters are received from station L7 and these address characters are again accumulated on the storage delay SD thereby forming a second address. For reasons which will be explained in detail later, the numbers stored on control delay CD are increased by one during each cycle. This is a very important point. As indicated in columns 10 and 12 of FIGURE 9, the number stored in character position one hundred and twelve (112) of transfer control delay CD is increased by one each cycle, that is, it is increased from four to five to six. When the third character of the second address is received, the address indicated thereby is stored in single character delay SCD6, which is the particular single character delay element then beginning a cycle. Again when the address stored in single character delay element SCD6 corresponds to the character position on the transport delay TD then appearing, the number of the single character delay element which will be associated with the originating input station during the next cycle of the transfer control delay CD is written on transfer control delay CD. In this case the address received (column 13) is the address of station L15. Position thirty-five (35) on the transport delay TD corresponds to station L15 (see column 15 of FIGURE 7). Character position thirty-five (35) on transport delay TD appears at the same time that character position one hundred and thirty (130) on control delay CD appears. Hence, the number of single character delay element SCDl is written in character position one hundred and thirty (130) on the control delay CD.

At the same time that the number of a single character delay element is written into a particular character position on control delay CD a bit is written into the position of storage delay SD then appearing. This bit is herein after called the reservation bit and as will be seen in detail later it is used to insure that only one message is transmitted to any particular output station at one particular time.

During each address setup mode a character is only written on a character position of control delay CD (as shown in columns 4 and 17 of FIGURE 9) if the reservation bit in the character position of the storage delay then appearing is not set indicating that no other message is currently being transmitted to the particular line.

As shown in FIGURE 2, after all of the addresses associated with a particular message are received the control character MCF is received. During the cycle following the reception of the control character MCF the system switches from the address mode to the message mode. This is accomplished by setting a control bit in the charactcr positions on the control delay CD wherein numbers of single character delay elements were written during the preceding address setup cycles. This is accomplished as follows. When the control character MCF is received the number of the single character delay element then be ginning a cycle is Written into itself. This is shown in column 19 of FIGURE 9, which shows what occurs when the control character MCF is received. At this time single character delay element SCDl is then beginning a cycle. Hence, the number of. single character delay SCDl is stored in single character delay element SCDl. This is indicated on line 50 of FIGURE 9.

During the next ninety-six (96) character times. the number stored in single character delay element SCDl is compared to the number read from transfer control element CD (i.e., the number stored during the previous cycle) and where there is a comparison a particular bit (called the activation bit) is set as indicated by the prime notation in line of FIGURE 9. In this case the number stored in single character delay element SCDI corresponds to the read from control delay element CD during character times one hundred and twelve (112) and one hundred and thirty (130). Hence, the activation bit is set in positions one hundred and twelve (112) and one hundred and thirty (130) on control delay element CD. Note that row 1a of FIGURE 9 shows the number written on control delay CD during the particular character times and this number is one higher than the number which is read from the control delay during the same character time. This will be explained in detail later.

During the next cycle the system is in message mode and the transfer of message characters as previously explained takes place.

Address erase mode After all of the characters of a particular message have been transferred the character EM appears. When this character appears the information stored on the control delay CD during the address setup mode which occurred at the beginning of the particular message must be de' leted or erased. Furthermore, the reservation bits stored on the storage delay element SD must be erased.

This is accomplished in substantially the same way that the activation bits were set on control delay CD (columns 19 to 24 of FIGURE 9). When the control character EM occurs the number of the particular single character delay element then in use is written into itself. During the next ninety-six (96) character times this number is compared to the number stored on the control delay CD. When coincidence occurs the number stored on the control delay, the associated activation bit and the reservation bit on the storage delay SD are all erased. At the end of an address erase mode all of the control information established during the address setup mode associated with the same message is therefore erased.

Inlerconnections between the major components in exchanger 102 The interconnections between the various components in the exchange 102 are shown in FIGURE 10. FIGURE 10 is a composite drawing which consists of FIGURES 10a and 10b. The details of the logic inside each of the various components will be explained later.

Recognition logic 1I0.-This logic examines the characters arriving on line 104. Message characters are trans mitted to control gate 113 via line A. address characters are transmitted to control gate 113 via line B. When a control character arrives by an input 104 recognition logic selectively activates C. D and E according to the pattern shown below.

Meaning of Character l Control gate 1I3.All of the message characters received by control gate 113 via line A are sent to the single character delay elements SCDl to SCD6 via line T3. Address characters received by control gate 113 are sometimes sent to the storage delay SD via line T2. As previously explained, each address is formed by three characters and the first two characters of an address are stored in storage delay SD until all of the three characters which form the address have been accumulated Thus. the first two characters of each address are sent to storage delay SD via line T2. These characters are returned to control gate 113 via line T1 at the proper time, that is at the same time that the third character of the address is arriving a control gate 113 via line B. After an address is accumulated, it is sent to the single character delay element SCDl to SCD6 via line T3. Control gate 113 receives inputs designated C and D from recognition logic 110. Line C indicates that the characters which follow are message characters and line D indicates that the end of the message has arrived. Thus, signals on lines C and D tell control gate 113 what to do with the characters arriving on lines A and B. Control gate 113 also has three inputs designated T11, T12 and T13 which come from the logic 111 which is associated with control delay CD. As previously explained, each address is formed by three address characters. A count of the number of address characters Which have already arrived is maintained in control delay CD (in a manner which will be explained in detail later), and the signals on lines T11, T12 and T13 indicate to control gate logic 113 whether the address character which it is then receiving is the first. second, or third character of an address. This information is conveyed to logic 112 via line T21.

Single character delay logic 107.The particular single character delay element SCD1 to SCD6 into which a message character or address is directed is controlled by logic 107. Single character delay elements SCD1 to SCD6 are assigned to the incoming character in reverse cyclic order. That is, if a first character is stored in single character delay element SCD1. the second character arriving is stored in single character delay ele ment SCD6, the third character is stored in single character delay element SCDS, etc. The result of the reverse cyclic order is that the characters from a particular line use the revolvers in forward cyclic order as previously explained (see FIGURE 7).

Characters on line T3 are directed into a particular single character delay element by multiplexing logical circuits 201 to 206. These circuits receive timing signals from timer 121 and in accordance with the timing signal assign the characters arriving on line T3 to a particular revolver. Logic 107 also controls the recycling of characters in single character delay elements SCD1 to SCD6. Each character which is stored in a single character delay element is recycled for ninety-six times. Multiplexing logic circuits 201 to 206 control the recycling operations in accordance with the signals received from timer 121.

The output of single character delay elements SCD1 to SCD6 appears on lines T31 to T36. Since each delay element only stores one character and since this character is continuously recycled therein until a new character is stored. the character stored in each delay element continually appears on the associated output line. As previously explained. each character consists of a seven bit. Thus, for example. if the character stored in single character delay element SCD1 consists of the seven bits a through g (as shown in FIGURE 4) the bits appearing on line T31 would be nbcdr'fg abcdefg, etc.

Transport delay logic I 09.Message characters appearing at the output of single character delay elements SCD1 to SCD6 are gated into transport delay element TD via transport delay logic 109. As previously explained, information stored on the control delay CD is used to control the transfer of characters from single character delay elements SCD1 to SCD6 into transport delay TD. Transport delay logic 109 receives signals from control delay CD via lines T14, T15, T16 and T17. Any information stored in transport delay TD is gated to output 105 when a character position in transport delay TD coincides with a line time. The gating of operation from transport delay logic TD to output 105 is controlled by timer 121. Each time that a line time signal appears on line L the character then appearing at the output of transport delay TD is gated from transport delay TD to output 105 by transport delay logic 109. The result is that the appropriate position on transport delay TD is always gated to output 105. For example, the coincidence of position sixty-six (66) on transport delay TD at line time eleven (11) (see column 11 in FIGURE 7) indicates that the machine is in character time one hundred and sixty-one (161) and that line time eleven (11) is being serviced. A line time never coincides with position sixty-six (66) on transport delay TD except during character time one hundred and sixty-one (161). Likewise, for each of the other positions on transport delay TD a line time will only coincide with the particular position when the associated line is being serviced.

Single character number comparator II5.-As previously explained when recognition logic 110 receives either control character MCF or control character EM, line C or D is activated and in response thereto single character revolver number comparator 115 compares the number stored in a selected one of the single character delay elements SCD1 to SCD6 to the numbers stored in the next ninety-six (96) character positions of the control delay CD. The signals which the single character revolver number comparator 115 generates when it detects coincidence between the number stored in the selected single character delay element and the numbers stored on the control delay CD, depend upon whether the system is in the address setup mode. or in the address erase mode. If the system is in the address setup mode and coincidence occurs, single character revolver number comparator 115 activates line T8 which sets the activation bit on control delay CD. If coincidence occurs during the address erase mode, single character revolver number comparator 115 activates lines T9 and T10. Activation of line T9 erases the reservation bit on the corresponding position in stor: age delay SD and activation of line T10, erases the num ber stored on the corresponding position of control delay CD. Single character revolver number comparator 115 includes six number comparator circuits 211 to 216. Each number comparator circuit 211 to 216 has five inputs, as follows:

(a) One of the lines T31 to T36 which supplies the number comparator logic with the output of one of the single character delay elements SCD1 to SCD6.

(c) Line D from recognition logic 110 which indicates whether the system is in address setup mode.

(c) Line D from recognition logic 110 which indicates whether the system is in address erase mode.

(d) An input T7 from control delay logic 111 which indicates the number stored in the character position of control delay CD then being read.

(e) Outputs from timer 121 which indicate which single character delay element should be read out.

The details of the logic in single character revolver number comparator circuits 211 to 216 will be described in detail later.

Queue identification r'ormrcr ]l9.This circuit generates the numbers 0 through 94. The numbers 0 through 94 in binary form are supplied on output T18. A dilierent number is supplied on output T18 during each character time. Thus. ninety-five diflerent numbers appear on line T18. Since storage delay SD and transport delay TD each have ninetyfive (95) character positions which sequentially appear, each number generated by queue identification counter 119 is uniquely associated with one character position in transport delay TD and one character position in storage delay SD. Each time a particular character position is read from transport delay TD, a corresponding position is read from storage delay SD and the address appears upon line T18.

The address of an input-output station is not the same as the binary representation of the number of the particular input-output station. The reason for this will be explained later. The address of input-output station L1 is 0000000, the address of input-output station L2 is 0010000, the address of input-output station L3 is 0100000. This is shown in columns 1 and 3 of FIGURE 11C. in general the address which designates each inputoutput station is the binary representation of the number which is one less than the number of the character position on transport delay TD, which is available during the same character time. For example the address of input-output station L11 is 1000001 (i.e., the binary number sixty-five) since character position sixty-six (see column 1 1, FIGURE 7) on transport delay TD is then available.

The reason that this is done is because queue identification counter 119 sequentially generates the numbers zero through ninety-four (0 to 94) during each ninety-five (95) character times while the character positions on transport delay TD appear sequentially. Since adjacent positions on transport delay TD are associated with line times which occur ninety seven (97) character times apart (see columns 1, 7 and 13 in FIGURE 7), the address of a line is different than its number. This com plication could be eliminated by renumbering the lines, however in such a case indicating the particular character time that each line was associated with, i.e., FIG- URE 3, would be much more complicated. 

1. A MESSAGE EXCHANGE SYSTEM COMPRISING AN INPUT FOR RECEIVING DATA CHARACTERS FROM A PLURALITY OF STATIONS ON A TIME MULTIPLEX BASIS, FIRST MEANS FOR SUPPLYING INFORMATION INDICATING THE DESIRED DESTINATION OF SAID CHARACTERS, A PLURALITY OF SINGLE CHARACTER DELAY ELEMENTS, A TRANSPORT DELAY ELEMENT HAVING ONE CHARACTER POSITION FOR EACH STATION, MEANS FOR STORING EACH MESSAGE CHARACTER IN A SINGLE CHARACTER DELAY ELEMENT AND FOR RECIRCULATING EACH MESSAGE CHARACTER THEREIN FOR ONE CYCLE OF SAID TRANSPORT DELAY ELEMENT, AND MEANS FOR TRANSFERRING MESSAGE CHARACTERS FROM SAID SINGLE CHARACTER DELAY ELEMENTS TO SAID TRANSPORT DELAY ELEMENT IN RESPONSE TO SAID FIRST MEANS. 